A semiconductor memory circuit (such as in Patent Document 1) is known in which bit lines are discharged to a ground potential before data is read from a memory cell is read, and a corresponding bit line is charged to a power supply potential at a time of reading data from the memory cell and data on the selected bit line is amplified by a sense amplifier. By discharging the bit lines to the ground (GND) potential, a drain-to-source leakage current in the memory cell including a cell transistor which has a drain connected to the corresponding bit line, can be restrained. FIG. 7 shows a configuration example of the semiconductor memory device disclosed in Patent Document 1. FIG. 7 shows ROM (Read Only Memory) memory cells and a read circuit of the ROM memory cells. Referring to FIG. 7, there are memory cells each including an NMOS transistor 1 which has a source electrode grounded, a drain electrode connected to a bit line, and a gate electrode connected to a word line, and memory cells each including an NMOS transistors 2 which has a floating source electrode, a drain electrode connected to a bit line, and a gate electrode connected to a word line. Each of dummy memory cells 3 which are replicas of the memory cells, has a source electrode grounded, a drain electrode connected to a bit line, and a gate electrode connected to a word line.
FIG. 8 is a timing chart showing a read operation of the semiconductor memory device in FIG. 7. In a time interval during which a signal RST is High, all bit lines B0 to Bn and a dummy bit line BD are discharged to a GND level through bit line discharging transistors 6. When the signal RST goes Low, the discharging transistors 6 are turned off. Next, one word line is selected by a row decoder 9, and goes High. Then, all the memory cells and one of the dummy cells 3 connected to the selected word line are turned on. A column select signal C0 goes High, the bit line B0 is connected to an input of a differential amplification sense amplifier circuit 18, and a signal PCR goes Low. Then, only a pair of the bit line B0 and the dummy bit line BD is charged through bit line charging transistors 5. In this case, when the source electrode of the selected memory cell is grounded (in the case of the memory cells 1), a potential at the bit line B0 is determined by a conductance ratio between the memory cell 1 and a bit line charging transistor 5. A potential at the dummy bit line BD that forms a pair with the bit line B0 is determined by a conductance ratio between the dummy cell 3 and a bit line charging transistor 5. Ordinarily, the conductance of the dummy memory cell 3 is set to be a half of that of the memory cell 1. Thus, the potential at the dummy bit line BD connected the dummy memory cell 3 is approximately doubled from the potential at the bit line B0 connected to the memory cell 1. Then, a potential difference is generated between inputs D and DDY of the differential amplification sense amplifier 18.
When the source electrode of the selected memory cell is floating (in the case of the memory cell 2), no current path is present. Thus, the bit line B0 is charged through the bit line charging transistor 5. In this case as well, a potential at the dummy bit line BD connected to the dummy memory cell 3 assumes a potential determined by the conductance ratio. Thus, the potential at the dummy bit line BD becomes lower than the potential at the bit line B0 to which the memory cell 2 is connected. For this reason, a potential difference is generated between the inputs D and DDY of the differential amplification sense amplifier circuit 18. The potential at the dummy bit line BD connected to the dummy memory cell 3 generates an intermediate reference potential between High and Low bit line potentials of an ordinary memory cell. Next, an enable signal SE goes High, the differential amplification sense amplifier circuit 18 is activated, an input minute potential difference is amplified, and data is output from an output buffer 19. As described above, the semiconductor memory circuit in FIG. 7 provides a reference signal that is intermediate between a read “1” and a read “0” using the dummy memory cell 3, and then amplifies a minute difference potential by the differential sense amplifier circuit 18, thereby performing a read operation.
As shown in FIG. 8, at a time of reading, the bit lines and the dummy bit line are first discharged to the GND potential. Then, a selected bit line and the dummy bit line are charged through the bit line charging transistors. Then, using a potential at the dummy bit line as a reference, differential amplification is performed by the differential amplification sense amplifier circuit 18.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-07-078489